1. Field of the Invention
This invention relates to an integrated circuit memory array, and more particularly to such an array wherein each individual memory cell is formed of a single transistor and a capacitive storage unit, the combination being referred to as a "single transistor cell."
2. Description of Prior Art
Many types of integrated circuit memories employing "single transistor cells" exist in the prior art. The advantage of "single transistor cells" is that less space per cell is required on an integrated circuit chip with the resultant higher packing density. A disadvantage of "single transistor cells" is that their charge must be restored or refreshed. Static memories which do not require a charge restore may be formed of memory cells each employing two or more transistors to form a latch. However, as the number of transistors per cell increases, a greater area is required for each cell with a resultant decrease in the cell packing density. A principal advantage of integrated circuitry formed on a semiconductor chip is that once the fabrication process has been developed, highly reliable circuits can be manufactured in volume to achieve an economy of scale. Thus, as the packing density of the circuit design increases, the manufacture of the resultant circuits becomes more economical.
The term "single transistor cell" is employed to mean a memory cell for storing a "0" or "1" binary bit of information, which cell employs no more than one transistor and also a capacitance. As was indicated above, "single transistor cells" have been employed in integrated circuit memories in order to achieve a higher cell packing density. The integrated circuit device may be a bipolar device; however, in the present invention, it is preferably an MOS device employing field effect transistors. An MOS (a metal-oxide semiconductor) device is a field effect transistor in which the silicon dioxide acts as a dielectric insulator between a gate contact metal and a substrate silicon channel. A field effect transistor, FET, is a solid-state device in which current is controlled between a source terminal and a drain terminal by a voltage applied to a nonconducting gate terminal.
Prior art disclosures of "single transistor cells" are contained, for example, in the Christensen, U.S. Pat. No. 3,588,844; Stein et al, U.S. Pat. No. 3,774,176; and Markowitz, U.S. Pat. No. 3,789,371.
The state of the art in integrated circuit memories has long been such that 1,024 bit cells could be placed on a single integrated circuit chip. In fact, the state of the art of integrated circuit technology is such that 4,096 bit cells can now be placed on an integrated circuit chip. However, to significantly increase the number of bit cells placed on an integrated circuit chip, certain problems must be overcome. The present invention is designed to provide an integrated circuit memory with 16,384 bit cells or more on an integrated circuit chip.
In the layout of memory circuits, consideration is to be given to the relation of the sense amplifiers to the various cells of the array. In one type of sensing arrangement, the respective sense amplifiers are placed in the middle of the array to service memory cells located in columns on both sides of the respective sense amplifiers. This provides an inherent differential balance with the result that signals of very small amplitude can be detected. This is particularly advantageous with "single transistor cells" memories. However, such a centered sensing method must be provided with compensation for capacitance imbalance. As distinct from the centered sensing method, sense amplifiers may be placed at one edge of the array with the cell accessing circuitry placed at the other edge of the array.
While differential sensing is required for signals of small amplitudes, physically locating sense amplifiers in the center of memory array becomes impractical when the number of cells in the array becomes increasingly large. It is desirable, then, to provide a large memory array with sense amplifiers located at one edge of the array which amplifiers nonetheless provide differential sensing and a completely balanced operation.
It is an object of the present invention to provide an improved and enlarged memory array on a single integrated circuit chip.
It is another object of present invention to provide an improved memory array the size of which can be increased without redesign of the array.
It is still another object of present invention to provide an improved and an enlarged memory array having sense amplifiers for differential sensing and balanced operation.